Vijayalakshmi (Viji) Srinivasan 
contact information
researchThomas J. Watson Research Center, Yorktown Heights, NY USA +1
9149451510
9149451510 links
2014
SQRL: Hardware Accelerator for Collecting Software Data Structures
S. Kumar, A. Shriraman, V. Srinivasan, D. Lin, and J. Philips
23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), 2014
Abstract
S. Kumar, A. Shriraman, V. Srinivasan, D. Lin, and J. Philips
23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), 2014
Abstract
NDC: Analyzing the Impact of 3D-Stacked Memory+ Logic Devices on MapReduce Workloads
Seth H Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, A Buyuktosunoglu, A Davis, F Li
International Symposium on Performance Analysis of Systems and Software, 2014
Seth H Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, A Buyuktosunoglu, A Davis, F Li
International Symposium on Performance Analysis of Systems and Software, 2014
2013
ReCaP: A Region-Based Cure for the Common Cold (Cache)
Jason Zebchuk, Harold W. Cain, Xin Tong, Vijayalakshmi Srinivasan, and Andreas Moshovos
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 83--94, 2013
Jason Zebchuk, Harold W. Cain, Xin Tong, Vijayalakshmi Srinivasan, and Andreas Moshovos
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 83--94, 2013
2012
Efficient scrub mechanisms for error-prone emerging memories
Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pp. 1--12
Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pp. 1--12
Programming with relaxed synchronization
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, Ravi Nair, and Daniel Prener
Proceedings of the 2012 ACM workshop on Relaxing synchronization for multicore and manycore scalability (RACES '12), pp. 41--50, ACM
Abstract
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, Ravi Nair, and Daniel Prener
Proceedings of the 2012 ACM workshop on Relaxing synchronization for multicore and manycore scalability (RACES '12), pp. 41--50, ACM
Abstract
2011
Handling PCM resistance drift with device, circuit, architecture, and system solutions
Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Rajeev Balasubramonian, Bipin Rajendran, Viji Srinivasan
Non-Volatile Memories Workshop, 2011
Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Rajeev Balasubramonian, Bipin Rajendran, Viji Srinivasan
Non-Volatile Memories Workshop, 2011
Relaxing Synchronization for Performance and Insight
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, Ravi Nair, Daniel Prener, Colin Blundell
IBM Research Report (RC25256), Technical Report RC25256, IBM, 2011
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, Ravi Nair, Daniel Prener, Colin Blundell
IBM Research Report (RC25256), Technical Report RC25256, IBM, 2011
SPATL : Honey, I Shrunk the Coherence Directory
Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan
The Twentieth International Conference on Parallel Architectures and Compilation Techniques, ACM/IEEE, 2011
Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan
The Twentieth International Conference on Parallel Architectures and Compilation Techniques, ACM/IEEE, 2011
2010
SAFER: Stuck-at-fault error recovery for memories
N H Seong, D H Woo, V Srinivasan, J A Rivers, H H S Lee
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 115--124
N H Seong, D H Woo, V Srinivasan, J A Rivers, H H S Lee
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 115--124
2009
A tagless coherence directory
J Zebchuk, V Srinivasan, M K Qureshi, A Moshovos
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 423--434, 2009
J Zebchuk, V Srinivasan, M K Qureshi, A Moshovos
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 423--434, 2009
Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling
M K Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 14--23, 2009
M K Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 14--23, 2009
Scalable high performance main memory system using phase-change memory technology
M K Qureshi, V Srinivasan, J A Rivers
Proceedings of the 36th annual international symposium on Computer architecture, pp. 24--33, 2009
M K Qureshi, V Srinivasan, J A Rivers
Proceedings of the 36th annual international symposium on Computer architecture, pp. 24--33, 2009
2008
Analyzing the Cost of a Cache Miss Using Pipeline Spectroscopy
T Puzak, A Hartstein, PG Emma, V Srinivasan, A Nadus
Journal of Instruction-Level Parallelism10, 1--33, 2008
T Puzak, A Hartstein, PG Emma, V Srinivasan, A Nadus
Journal of Instruction-Level Parallelism10, 1--33, 2008
On the nature of cache miss behavior: Is it√ 2
A Hartstein, V Srinivasan, T Puzak, P Emma
The Journal of Instruction-Level Parallelism10, 2008
A Hartstein, V Srinivasan, T Puzak, P Emma
The Journal of Instruction-Level Parallelism10, 2008
2007
An analysis of the effects of miss clustering on the cost of a cache miss
T R Puzak, A Hartstein, PG Emma, V Srinivasan, J Mitchell
Proceedings of the 4th international conference on Computing frontiers, pp. 3--12, 2007
T R Puzak, A Hartstein, PG Emma, V Srinivasan, J Mitchell
Proceedings of the 4th international conference on Computing frontiers, pp. 3--12, 2007
Pipeline spectroscopy
T R Puzak, A Hartstein, V Srinivasan, PG Emma, A Nadas
Performance Evaluation Review 35(1), 351, ACM ASSOCIATION FOR COMPUTING MACHINERY, 2007
T R Puzak, A Hartstein, V Srinivasan, PG Emma, A Nadas
Performance Evaluation Review 35(1), 351, ACM ASSOCIATION FOR COMPUTING MACHINERY, 2007
2006
Measuring the cost of a cache miss
T Puzak, Allan Hartstein, P Emma, Viji Srinivasan
Workshop on Modeling, Benchmarking and Simulation (MoBS), 2006
T Puzak, Allan Hartstein, P Emma, Viji Srinivasan
Workshop on Modeling, Benchmarking and Simulation (MoBS), 2006
Cache miss behavior: is it√ 2?
A Hartstein, V Srinivasan, T R Puzak, P G Emma
Proceedings of the 3rd conference on Computing frontiers, pp. 313--320, 2006
A Hartstein, V Srinivasan, T R Puzak, P G Emma
Proceedings of the 3rd conference on Computing frontiers, pp. 313--320, 2006
2005
Cache Design Options for a Clustered Multithreaded Architecture
Rajeev Garg, Ali El-Moursy, Sandhya Dwarkadas, David Albonesi, Jude Rivers, Viji Srinivasan
2005 - urresearch.rochester.edu
Rajeev Garg, Ali El-Moursy, Sandhya Dwarkadas, David Albonesi, Jude Rivers, Viji Srinivasan
2005 - urresearch.rochester.edu
The case for microarchitectural awareness of lifetime reliability
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude Rivers, Y Li, D Brooks, Z Hu, K Skadron, V Srinivasan, M Gschwind, others
IEEE Micro 25(3), 70--80, 2005
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude Rivers, Y Li, D Brooks, Z Hu, K Skadron, V Srinivasan, M Gschwind, others
IEEE Micro 25(3), 70--80, 2005
When prefetching improves/degrades performance
Thomas R Puzak, A Hartstein, P G Emma, V Srinivasan
Proceedings of the 2nd conference on Computing frontiers, pp. 342--352, ACM, 2005
Abstract
Thomas R Puzak, A Hartstein, P G Emma, V Srinivasan
Proceedings of the 2nd conference on Computing frontiers, pp. 342--352, ACM, 2005
Abstract
Exploring the limits of prefetching
P G Emma, A Hartstein, T R Puzak, V Srinivasan
IBM Journal of Research and Development 49(1), 127--144, International Business Machines Corp, Old Orchard Rd, Armonk, NY, 10504, USA, 2005
P G Emma, A Hartstein, T R Puzak, V Srinivasan
IBM Journal of Research and Development 49(1), 127--144, International Business Machines Corp, Old Orchard Rd, Armonk, NY, 10504, USA, 2005
2004
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches
R Balasubramonian, V Srinivasan, S Dwarkadas, A Buyuktosunoglu
Power-aware computer systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003: revised papers, pp. 180, 2004
R Balasubramonian, V Srinivasan, S Dwarkadas, A Buyuktosunoglu
Power-aware computer systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003: revised papers, pp. 180, 2004
A prefetch taxonomy
V Srinivasan, ES Davidson, GS Tyson
IEEE Transactions on Computers 53(2), 126--140, 2004
V Srinivasan, ES Davidson, GS Tyson
IEEE Transactions on Computers 53(2), 126--140, 2004
Integrated analysis of power and performance for pipelined microprocessors
P. Bose, D. Brooks, P. Emma, M. Gschwind, V. Srinivasan, P. Strenski, V. Zyuban
IEEE Transactions on Computers 53(8), 1004--1016, IEEE, 2004
P. Bose, D. Brooks, P. Emma, M. Gschwind, V. Srinivasan, P. Strenski, V. Zyuban
IEEE Transactions on Computers 53(8), 1004--1016, IEEE, 2004
Microarchitectural techniques for power gating of execution units
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, Pradip Bose
Proceedings of the 2004 international symposium on Low power electronics and design, pp. 32--37
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, Pradip Bose
Proceedings of the 2004 international symposium on Low power electronics and design, pp. 32--37
2003
Microarchitecture-level power-performance analysis: the powertimer approach
David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, P Emma, M Rosenfield
IBM J. Research and Development 47(5/6), 653--670, 2003
David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, P Emma, M Rosenfield
IBM J. Research and Development 47(5/6), 653--670, 2003
Early-stage definition of LPX: A low power issue-execute processor
P Bose, D Brooks, A Buyuktosunoglu, P Cook, K Das, P Emma, M Gschwind, H Jacobson, T Karkhanis, P Kudva
Power-Aware Computer Systems, pp. 89--92, Springer, 2003
P Bose, D Brooks, A Buyuktosunoglu, P Cook, K Das, P Emma, M Gschwind, H Jacobson, T Karkhanis, P Kudva
Power-Aware Computer Systems, pp. 89--92, Springer, 2003
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
David Brooks, Pradip Bose, Viji Srinivasan, MK Gschwind, Philip G Emma, Michael G Rosenfield
IBM Journal of Research and Development 47(5.6), 653--670, IBM, 2003
David Brooks, Pradip Bose, Viji Srinivasan, MK Gschwind, Philip G Emma, Michael G Rosenfield
IBM Journal of Research and Development 47(5.6), 653--670, IBM, 2003
Branch history guided instruction/data prefetching
T R Puzak, A M Hartstein, M Charney, D A Prener, P H Oden, V Srinivasan
US Patent ..., 2003 - Google Patents, Google Patents
US Patent 6,560,693
T R Puzak, A M Hartstein, M Charney, D A Prener, P H Oden, V Srinivasan
US Patent ..., 2003 - Google Patents, Google Patents
US Patent 6,560,693
2002
Optimizing pipelines for power and performance
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, Philip G Emma
Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on, pp. 333--344
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, Philip G Emma
Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on, pp. 333--344
2001
Branch history guided instruction prefetching
V Srinivasan, E S Davidson, G S Tyson, M J Charney, T R Puzak
hpca, pp. 0291, 2001
V Srinivasan, E S Davidson, G S Tyson, M J Charney, T R Puzak
hpca, pp. 0291, 2001
2000
SpliCS-Split Latency Cache System
V Srinivasan, M J Charney, E S Davidson, G S Tyson
2000 - Citeseer, Citeseer
V Srinivasan, M J Charney, E S Davidson, G S Tyson
2000 - Citeseer, Citeseer
1999
Active management of data caches by exploiting reuse information
E S Tam, J A Rivers, V Srinivasan, G S Tyson, E S Davidson
IEEE Transactions on Computers 48(11), 1244--1259, 1999
E S Tam, J A Rivers, V Srinivasan, G S Tyson, E S Davidson
IEEE Transactions on Computers 48(11), 1244--1259, 1999
1998
Improving performance of an L1 cache with an associated buffer
Vijayalakshmi Srinivasan
Technical ReportCSE-TR-361-98, Universityof Michigan Departmentof Electrical Engineering and Computer Science, Citeseer, 1998
Vijayalakshmi Srinivasan
Technical ReportCSE-TR-361-98, Universityof Michigan Departmentof Electrical Engineering and Computer Science, Citeseer, 1998
Evaluating the performance of active cache management schemes
E S Tam, J A Rivers, V Srinivasan, G S Tyson, E S Davidson
Computer Design: VLSI in Computers and Processors, 1998, pp. 368--375
E S Tam, J A Rivers, V Srinivasan, G S Tyson, E S Davidson
Computer Design: VLSI in Computers and Processors, 1998, pp. 368--375
Improving performance of an L1 cache with an associated buffer
V Srinivasan
Technical ReportCSE-TR-361-98, Universityof Michigan Departmentof Electrical Engineering and Computer Science, Citeseer, 1998
V Srinivasan
Technical ReportCSE-TR-361-98, Universityof Michigan Departmentof Electrical Engineering and Computer Science, Citeseer, 1998
1997
Towards a communication characterization methodology for parallel applications
S Chodnekar, V Srinivasan, A S Vaidya, A Sivasubramaniam, C R Das
hpca, pp. 310, 1997
S Chodnekar, V Srinivasan, A S Vaidya, A Sivasubramaniam, C R Das
hpca, pp. 310, 1997