Vijayalakshmi (Viji) Srinivasan 
contact information
researchThomas J. Watson Research Center, Yorktown Heights, NY USA +1
9149451510
9149451510 links
2013
Adaptive multi-bit error correction in endurance limited memories
Jude A Rivers, Vijayalakshmi Srinivasan
US Patent 8,589,762
Jude A Rivers, Vijayalakshmi Srinivasan
US Patent 8,589,762
Write-through cache optimized for dependence-free parallel regions
Alexandre E Eichenberger, Alan G Gara, Martin Ohmacht, Vijayalakshmi Srinivasan
US Patent 8,516,197
Alexandre E Eichenberger, Alan G Gara, Martin Ohmacht, Vijayalakshmi Srinivasan
US Patent 8,516,197
Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history
Philip G Emma, Allan M Hartstein, Brian R Prasky, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent 8,521,999
Philip G Emma, Allan M Hartstein, Brian R Prasky, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent 8,521,999
Non-data inclusive coherent (nic) directory for cache
Timothy C Bronson, Garrett M Drapala, Rebecca M Gott, Pak-Kin Mak, Vijayalakshmi Srinivasan, Craig R Walters
US Patent App. 13/784,958
Timothy C Bronson, Garrett M Drapala, Rebecca M Gott, Pak-Kin Mak, Vijayalakshmi Srinivasan, Craig R Walters
US Patent App. 13/784,958
2012
Multi-threaded processor instruction balancing through instruction uncertainty
Alper Buyuktosunoglu, Brian R Prasky, Vijayalakshmi Srinivasan
US Patent App. 13/366,999
Alper Buyuktosunoglu, Brian R Prasky, Vijayalakshmi Srinivasan
US Patent App. 13/366,999
Methods of cache preloading on a partition or a context switch
Harold W Cain III, Vijayalakshmi Srinivasan, Jason Zebchuk
US Patent App. 13/545,304
Harold W Cain III, Vijayalakshmi Srinivasan, Jason Zebchuk
US Patent App. 13/545,304
Structure for implementing dynamic refresh protocols for DRAM based cache
John E Barth, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,108,609
John E Barth, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,108,609
2011
Method and system for integrating SRAM and DRAM architecture in set associative cache
Marc R Faucher, Hillery C Hunter, William R Reohr, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 7,962,695
Marc R Faucher, Hillery C Hunter, William R Reohr, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 7,962,695
Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor
Ioana Monica Burcea, Alper Buyuktosunoglu, Brian Robert Prasky, Vijayalakshmi Srinivasan
US Patent App. 13/172,218
Ioana Monica Burcea, Alper Buyuktosunoglu, Brian Robert Prasky, Vijayalakshmi Srinivasan
US Patent App. 13/172,218
Method and apparatus for an efficient multi-path trace cache design
Galen A Rasche, Jude A Rivers, Vijayalakshmi Srinivasan
US Patent 7,958,334
Galen A Rasche, Jude A Rivers, Vijayalakshmi Srinivasan
US Patent 7,958,334
Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class
Erik R Altman, Vijayalakshmi Srinivasan
US Patent 7,971,033
Erik R Altman, Vijayalakshmi Srinivasan
US Patent 7,971,033
Predicting cache misses using data access behavior and instruction address
Vijayalakshmi Srinivasan, Brian R Prasky
US Patent App. 13/099,178
Vijayalakshmi Srinivasan, Brian R Prasky
US Patent App. 13/099,178
Relaxation of synchronization for iterative convergent computations
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan
US Patent App. 13/184,718
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan
US Patent App. 13/184,718
Method and system for providing an improved store-in cache
Philip George Emma, Wing K Luk, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent 7,941,728
Philip George Emma, Wing K Luk, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent 7,941,728
Method and system for implementing dynamic refresh protocols for DRAM based cache
John E Barth Jr, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,024,513
John E Barth Jr, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,024,513
Iterative write pausing techniques to improve read latency of memory systems
Michele M Franceschini, Luis A Lastras-Montano, Moinuddin K Qureshi, Vijayalakshmi Srinivasan
US Patent 8,004,884
Michele M Franceschini, Luis A Lastras-Montano, Moinuddin K Qureshi, Vijayalakshmi Srinivasan
US Patent 8,004,884
Method and system for preventing livelock due to competing updates of prediction information
E R Altman, V Srinivasan, others
US Patent 7,979,682
E R Altman, V Srinivasan, others
US Patent 7,979,682
Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers
E R Altman, V Srinivasan
US Patent 7,966,478
E R Altman, V Srinivasan
US Patent 7,966,478
2010
Cache Line Replacement In A Symmetric Multiprocessing Computer
Vijayalakshmi Srinivasan, Craig Walters
US Patent App. 12/821,827
Vijayalakshmi Srinivasan, Craig Walters
US Patent App. 12/821,827
Prefetching branch prediction mechanisms
Philip G Emma, Allan M Hartstein, Brian R Prasky, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent App. 12/721,933
Philip G Emma, Allan M Hartstein, Brian R Prasky, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent App. 12/721,933
2009
Processor Core Stacking for Efficient Collaboration
Philip G Emma, Eren Kursun, Moin K Qureshi, Viji Srinivasan
US Patent App. 12/570,351
Philip G Emma, Eren Kursun, Moin K Qureshi, Viji Srinivasan
US Patent App. 12/570,351
Method and apparatus for prefetching branch history information
Philip G Emma, Klaus J Getzlaff, Allan M Hartstein, Thomas Pflueger, Thomas R Puzak, Eric Mark Schwarz, Vijayalakshmi Srinivasan
US Patent 7,493,480
Philip G Emma, Klaus J Getzlaff, Allan M Hartstein, Thomas Pflueger, Thomas R Puzak, Eric Mark Schwarz, Vijayalakshmi Srinivasan
US Patent 7,493,480
Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor
E R Altman, V Srinivasan
US Patent 7,516,310
E R Altman, V Srinivasan
US Patent 7,516,310
2008
Embedded dram having multi-use refresh cycles
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/019,818
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/019,818
Design structure for an embedded dram having multi-use refresh cycles
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/103,290
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/103,290
Methods involving memory caches
Philip G Emma, Robert K Montoye, Vijayalakshmi Srinivasan
US Patent 7,472,226
Philip G Emma, Robert K Montoye, Vijayalakshmi Srinivasan
US Patent 7,472,226
Context look ahead storage structures
Philip George Emma, Allan Mark Hartstein, Brian R Prasky, Thomas Roberts Puzak, Moinuddin Khalil Ahmed Qureshi, Vijayalakshmi Srinivasan
US Patent 7,337,271
Philip George Emma, Allan Mark Hartstein, Brian R Prasky, Thomas Roberts Puzak, Moinuddin Khalil Ahmed Qureshi, Vijayalakshmi Srinivasan
US Patent 7,337,271
Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power
Pradip Bose, Alper Buyuktosunoglu, Zhigang Hu, Hans Mikael Jacobson, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,447,923
Pradip Bose, Alper Buyuktosunoglu, Zhigang Hu, Hans Mikael Jacobson, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,447,923
COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS
A Buyuktosunoglu, Z Hu, J A Rivers, J T Robinson, X Shen, V Srinivasan
US Patent App. 20,090/083,492
A Buyuktosunoglu, Z Hu, J A Rivers, J T Robinson, X Shen, V Srinivasan
US Patent App. 20,090/083,492
Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction
E R Altman, V Srinivasan
US Patent 7,401,209
E R Altman, V Srinivasan
US Patent 7,401,209
2006
Means for supporting and tracking a large number of in-flight stores in an out-of-order processor
Erik R Altman, Vijayalakshmi Srinivasan
US Patent App. 11/428,582
Erik R Altman, Vijayalakshmi Srinivasan
US Patent App. 11/428,582
Processor with low overhead predictive supply voltage gating for leakage power reduction
P Bose, D M Brooks, P W Cook, P G Emma, M K Gschwind, S E Schuster, V Srinivasan
US Patent 7,134,028
P Bose, D M Brooks, P W Cook, P G Emma, M K Gschwind, S E Schuster, V Srinivasan
US Patent 7,134,028
MEANS FOR SUPPORTING AND TRACKING A LARGE NUMBER OF IN-FLIGHT LOADS IN AN OUT-OF-ORDER PROCESSOR
E R Altman, V Srinivasan
US Patent App. 20,080/010,441
E R Altman, V Srinivasan
US Patent App. 20,080/010,441
2005
Handling permanent and transient errors using a SIMD unit
Erik Altman, Gheorghe Cascaval, Luis Ceze, Vijayalakshmi Srinivasan
US Patent App. 11/063,122
Erik Altman, Gheorghe Cascaval, Luis Ceze, Vijayalakshmi Srinivasan
US Patent App. 11/063,122
Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures
A Buyuktosunoglu, Z Hu, J A Rivers, J T Robinson, X Shen, V Srinivasan
US Patent App. 20,060/248,287
A Buyuktosunoglu, Z Hu, J A Rivers, J T Robinson, X Shen, V Srinivasan
US Patent App. 20,060/248,287
2003
Branch history guided instruction/data prefetching
Thomas R Puzak, Allan M Hartstein, Mark Charney, Daniel A Prener, Peter H Oden, Vijayalakshmi Srinivasan
US Patent 6,560,693
Thomas R Puzak, Allan M Hartstein, Mark Charney, Daniel A Prener, Peter H Oden, Vijayalakshmi Srinivasan
US Patent 6,560,693
2002
Two dimensional branch history table prefetching mechanism
Philip Emma, Klaus Getzlaff, Allan Hartstein, Thomas Pflueger, Thomas Puzak, Eric Schwarz, Vijayalakshmi Srinivasan
Philip Emma, Klaus Getzlaff, Allan Hartstein, Thomas Pflueger, Thomas Puzak, Eric Schwarz, Vijayalakshmi Srinivasan