Huiming Bu

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- - Chung-Hsun Lin
  - Wilfried Haensch
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- - Q. Liu
  - Frederic Monsieur
  - et al.
- 2011
- VLSI Technology 2011
Cold (100°C) carbon co-implantation into high phosphorus doping source/drain extensions for aggressively scaled NFETs
- - Koichi Yako
  - Makoto Fujiwara
  - et al.
- 2011
- IWJT 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
Ultra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology
- - Q. Liu
  - A. Yagishita
  - et al.
- 2011
- CSTIC 2011
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- - Kingsuk Maitra
  - Ali Khakifirooz
  - et al.
- 2011
- IEEE Electron Device Letters
High-performance partially depleted SOI PFETs with in situ doped sige raised source/drain and implant-free extension
- - Ali Khakifirooz
  - Kangguo Cheng
  - et al.
- 2011
- IEEE Electron Device Letters

Patents

- 01 Jan 2013
- US
- 8344428
Nanopillar E-fuse Structure And Process
- 27 Nov 2012
- US
- 8318565
High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof
- 16 Oct 2012
- US
- 8288218
Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors
- 04 Sep 2012
- US
- 8258037
Nanopillar Decoupling Capacitor
- 17 Jan 2012
- US
- 8097520
Integration Of Passive Device Structures With Metal Gate Layers
- 11 Oct 2011
- US
- 8035173
Cmos Transistors With Differential Oxygen Content High-k Dielectrics
- 17 May 2011
- US
- 7943460
High-k Metal Gate Cmos
- 04 Jan 2011
- US
- 7863123
Direct Contact Between High-k/metal Gate And Wiring Process Flow
- 08 Dec 2010
- CN
- ZL200810125977.0
Cmos Transistors With Differential Oxygen Content High-k Dielectrics
- 13 Apr 2010
- US
- 7696036
Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Top collaborators

Huiming Bu

Title

Bio

Publications

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell

Impact of back bias on ultra-thin body and BOX (UTBB) devices

Cold (100°C) carbon co-implantation into high phosphorus doping source/drain extensions for aggressively scaled NFETs

Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology

Ultra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology

Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications

High-performance partially depleted SOI PFETs with in situ doped sige raised source/drain and implant-free extension

Patents

Nanopillar E-fuse Structure And Process

High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof

Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors

Nanopillar Decoupling Capacitor

Integration Of Passive Device Structures With Metal Gate Layers

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

High-k Metal Gate Cmos

Direct Contact Between High-k/metal Gate And Wiring Process Flow

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Top collaborators

Dechao Guo

Dan J. Dechene

Hemanth Jagannathan

Nick Lanzillo