Tenko Yamashita

Title

Senior Manager - Advanced Logic Pathfinding Technology

Bio

Tenko Yamashita is a principal research scientist and senior manager in the advanced logic pathfinding organization at IBM Research. He is currently leading the CMOS technology research for 1nm and beyond and driving the long-term CMOS transistor roadmap for IBM and for the joint research partners.

Since joined IBM research at Albany in 2009, Tenko has been working on FinFET, Nanosheet, VTFET and recently he is working on the 3D stacked transistors and the advanced interconnect technologies. He has received several Outstanding Technical Achievement Awards (OTAA), Research Division Awards (RDA) for his technical contributions to the early transistor technology developments. Tenko is the recipient of the IBM corporate award, The Best of IBM in 2019 for his contribution to FinFET technology research and IBM Z15 productization.

Tenko has authored or co-authored more than 45 papers in the major semiconductor conferences i.e. IEDM, VLSI Symposium etc and IEEE journals. Tenko is a member of IEEE and currently he is the ALT sub-committee member of IEDM from 2023.

Tenko graduated from Kyushu University, Fukuoka, Japan with a master's degree in physics in 1992.

Publications

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- - Abhijeet Paul
  - Andres Bryant
  - et al.
- 2013
- IEDM 2013
Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs
- - Abhijeet Paul
  - Chun-Chen Yeh
  - et al.
- 2013
- S3S 2013
Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs
- - A. Khakifirooz
  - R. Sreenivasan
  - et al.
- 2013
- S3S 2013
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- - S. Lee
  - Richard A. Wachnik
  - et al.
- 2013
- VLSI Technology 2013
Channel doping impact on FinFETs for 22nm and beyond
- - Chung-Hsun Lin
  - R. Kambhampati
  - et al.
- 2012
- VLSI Technology 2012
Analysis of parasitic resistance in double gate FinFETs with different fin lengths
- - X. Yang
  - Kingsuk Maitra
  - et al.
- 2011
- IEEE International SOI Conference 2011
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- - Chung-Hsun Lin
  - Wilfried Haensch
  - et al.
- 2011
- VLSI Technology 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010

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Patents

- 19 Mar 2018
- US
- 9923055
Inner Spacer For Nanosheet Transistors
- 19 Mar 2018
- US
- 9922942
Support For Long Channel Length Nanowire Transistors
- 12 Mar 2018
- US
- 9917162
Fabrication Of Vertical Field Effect Transistor Structure With Controlled Gate Length
- 12 Mar 2018
- US
- 9917081
Semiconductor Device Including Finfet And Fin Varactor
- 12 Mar 2018
- US
- 9917152
Nanosheet Transistors On Bulk Material
- 05 Mar 2018
- US
- 9911657
Semiconductor Device Including Finfet And Fin Varactor
- 26 Feb 2018
- US
- 9905671
Forming A Gate Contact In The Active Area
- 26 Feb 2018
- US
- 9905665
Replacement Metal Gate Stack For Diffusion Prevention
- 19 Feb 2018
- US
- 9899373
Forming Vertical Transistors And Metal-insulator-metal Capacitors On The Same Chip
- 19 Feb 2018
- US
- 9899524
Split Fin Field Effect Transistor Enabling Back Bias On Fin Type Field Effect Transistors

Top collaborators

Tenko Yamashita

Title

Bio

Publications

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs

Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices

Channel doping impact on FinFETs for 22nm and beyond

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology

A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Patents

Inner Spacer For Nanosheet Transistors

Support For Long Channel Length Nanowire Transistors

Fabrication Of Vertical Field Effect Transistor Structure With Controlled Gate Length

Semiconductor Device Including Finfet And Fin Varactor

Nanosheet Transistors On Bulk Material

Semiconductor Device Including Finfet And Fin Varactor

Forming A Gate Contact In The Active Area

Replacement Metal Gate Stack For Diffusion Prevention

Forming Vertical Transistors And Metal-insulator-metal Capacitors On The Same Chip

Split Fin Field Effect Transistor Enabling Back Bias On Fin Type Field Effect Transistors

Top collaborators

Dechao Guo

Huiming Bu

Dan J. Dechene

Nicolas Loubet