Conference paper
Sub-15 ps charge-buffered active-pull-down ECL/NTL circuits
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
R. Puri, C.T. Chuang
VLSID 2000
P.F. Lu, C.T. Chuang
CICC 1992
X. Liu, A. Petrou, et al.
Applied Physics Letters