B. Davari, C. Koburger, et al.
IEDM 1989
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
B. Davari, C. Koburger, et al.
IEDM 1989
B.S. Wu, C.T. Chuang, et al.
CICC 1992
D.D. Awschalom, J. Warnock, et al.
QELS 1989
C.T. Chuang, P.F. Lu
IEDM 1989