Conference paper
High-speed low-power cross-coupled active-pull-down ECL circuit
C.T. Chuang, B.S. Wu, et al.
BCTM 1993
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
C.T. Chuang, B.S. Wu, et al.
BCTM 1993
Keith A. Jenkins, J.D. Cressler, et al.
IEDM 1991
W.C. Chou, A. Twardowski, et al.
Journal of Applied Physics
W.C. Chou, A. Petrou, et al.
Physical Review B