Conference paper
A 1.9 ns/6.3 W/256 Kb bipolar SRAM design
Kai-Yap Toh, C.T. Chuang, et al.
Bipolar Circuits and Technology Meeting 1990
The effects of gate tunneling current on high performance, static random access memory (SRAM) designed in bulk complementary metal oxide semiconductor (CMOS) technology were described. The SRAMs, fabricated by using partially depleted silicon on insulator (PD-SOI) technology, achieved 2.0 GHz cycle time and 430 picosecond access time. The memory utilized pseudo-static circuits for robust timing and to facilitate migration to PD/SOI technology.
Kai-Yap Toh, C.T. Chuang, et al.
Bipolar Circuits and Technology Meeting 1990
C.T. Chuang, Ken Chin, et al.
IEEE Journal of Solid-State Circuits
R.V. Joshi, Y. Chan, et al.
IEEE SOI 2006
L.J. Huang, J.O. Chu, et al.
VLSI Technology 2001