Jessie Rosenberg, William M. J. Green, et al.
OFC 2011
A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-μm SiGe BiCMOS technology featuring 120-GHz fT and 100 GHz fmax. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10-9 is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a - 3. 6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a - 3.6-V supply voltage.
Jessie Rosenberg, William M. J. Green, et al.
OFC 2011
Mark Ferriss, Bodhisatwa Sadhu, et al.
ISSCC 2016
Daniel M. Kuchta, Clint Schow, et al.
OFC 2013
Philippe André, Jean-Louis Benchimol, et al.
IEEE Journal of Solid-State Circuits