Gautam R. Gangasani, Chun-Ming Hsu, et al.
IEEE JSSC
This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16GFC and consumes 385 m W/link. © 2012 IEEE.
Gautam R. Gangasani, Chun-Ming Hsu, et al.
IEEE JSSC
Azita Emami-Neyestanak, Aida Varzaghani, et al.
IEEE Journal of Solid-State Circuits
John F. Bulzacchelli, Zeynep Toprak-Deniz, et al.
IEEE Journal of Solid-State Circuits
Timothy O. Dickson, Zeynep Toprak Deniz, et al.
IEEE JSSC