Conference paper
Testing and debugging delay faults in dynamic circuits
Ramyanshu Datta, Sani Nassif, et al.
IEEE ITC 2005
Paper
A 270ps 20mW 108-bit end-around carry adder for multiply-add fused floating point unit
Abstract
A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply. © 2008 Springer Science+Business Media, LLC.
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