A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
- Yong Liu
- Ping-Hsuan Hsieh
- et al.
- 2013
- ISSCC 2013
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34 results for Robert Montoye
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
- Gary S. Ditlow
- Robert K. Montoye
- et al.
- 2011
- ISSCC 2011
A double precision floating point multiply
- Robert Montoye
- Wendy Belluomini
- et al.
- 2003
- ISSCC 2003
An 18 ns 56-bit multiply-adder circuit
- Robert K. Montoye
- P.W. Cook
- et al.
- 1990
- ISSCC 1990
1 Mb 0.41 μm2; 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert K. Montoye
- et al.
- 2014
- IEEE JSSC
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
Matrix-matrix multiplication on a large register file architecture with indirection
- Dheeraj Sreedhar
- J.H. Derby
- et al.
- 2014
- HiPC 2014
Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure
- D. Sreedhar
- J.H. Derby
- et al.
- 2013
- ICASSP 2013
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Circuits 2013
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Technology 2013