Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
A 2:1 multiplexer with built-in 1-tap FFE is designed in a SiGe technology with fr of 210 GHz and fMAX of 260 GHz. The FFE is implemented with a delay and a secondary selector. The circuit is able to equalize cable loss of up to 12 dB at 90 Gb/s and 14 dB at 80 Gb/s, while operating from a -3.3 V supply. Error-free operation of the MUX was verified with 231-1 PRBS up to 40 Gb/s, which is the limit of the available error detector. © 2008 IEEE.
Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
Ekaterina Laskin, Alexander Rylyakov
SiRF 2009
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OFC 2013
Solomon Assefa, William M. J. Green, et al.
IPC 2012