Phillip J. Restle, Craig A. Carter, et al.
Digest of Technical Papers-IEEE International Solid-State Circuits Conference
A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50 000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured.
Phillip J. Restle, Craig A. Carter, et al.
Digest of Technical Papers-IEEE International Solid-State Circuits Conference
Phillip J. Restle, Craig A. Carter, et al.
ISSCC 2002
Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits
Alina Deutsch, Gerard V. Kopcsay, et al.
IEEE T-MTT