Pravein Govindan Kannan, Brent Salisbury, et al.
arXiv
This brief presents an RFSoC-based functional verification platform for a 2-lane pulse amplitude modulation (PAM) transceiver (TRX) datapath supporting 4-level PAM (PAM-4) and 8-level PAM (PAM-8). Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) existing on the ZU28DR RFSoC are used as digital front-ends of the transmitter (TX) and the receiver (RX), respectively. All digital equalization circuits and adaptation engines required for the modern > 112Gb/s DAC/ADC-DSP-based TRX datapath (excluding clock recovery) are implemented on the programmable logic (PL) running at 50 MHz, enabling real-time functional verification of the DAC/ADC-DSP-based serializer-deserializer (SerDes) operation. The register-transfer-level (RTL) design of the DSP can be directly used for the TRX silicon tape-out once the design is verified with the proposed RFSoC-based platform. The proposed system demonstrates a complete real-time functional verification of the TRX datapath, including the bit-error-rate (BER) test with the BER lower than 10-9 at 6.4Gb/s and 9.6Gb/s for PAM-4/8 symbols, respectively, with a channel loss of 18 dB at 1.6 GHz.
Pravein Govindan Kannan, Brent Salisbury, et al.
arXiv
Alex Merenstein, Vasily Tarasov, et al.
SYSTOR 2023
Marcelo Amaral, Sunyanan Choochotkaew
KubeCon EU 2024
Anthony Saporito
Hot Chips 32