Optimizing history effects in 65nm PD-SOI CMOS
Q. Liang, T. Kawamura, et al.
IEEE International SOI Conference 2006
This letter describes the first system level test vehicle in Josephson technology. The experiment consists of four circuit chips assembled on two cards in a high density, 3-dimensional, card-on-board package. A data path, which is representative of a critical path of a future prototype processor, was successfully operated with a minimum cycle time of 3.7ns. The path simulates a jump control sequence and a cache access in each machine cycle. This experiment incorporates the essential components of the logic, power and package portions of a Josephson technology prototype. Copyright © 1981 by The Institute of Electrical and Electronics Engineers, Inc.
Q. Liang, T. Kawamura, et al.
IEEE International SOI Conference 2006
M.B. Ketchen
IEEE Transactions on Magnetics
M. Steffen, David P. Divincenzo, et al.
IBM J. Res. Dev
J. Matisoo
IEEE Transactions on Magnetics