Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates
- Mark B. Ketchen
- Manjul Bhushan
- et al.
- 2004
- Review of Scientific Instruments
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26 results for C.J. Anderson
The circuit and physical design of the POWER4 microprocessor
- J. Warnock
- J. Keaty
- et al.
- 2002
- IBM J. Res. Dev
Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially depleted SOI devices
- C.T. Chuang
- P.F. Lu
- et al.
- 1999
- International Journal of Electronics
Metastability of SOI CMOS latches
- Christophe R. Tretz
- C.T. Chuang
- et al.
- 1999
- International Journal of Electronics
SOI for digital CMOS VLSI: Design considerations and advances
- Ching-T.E. Chuang
- L.U. Pong-Fei
- et al.
- 1998
- Proceedings of the IEEE
A 400-MHz S/390 microprocessor
- Charles F. Webb
- Carl J. Anderson
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Floating-body effects in partially depleted SOI CMOS circuits
- Pong-Fei Lu
- Ching-Te Chuang
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices
- C.T. Chuang
- P.F. Lu
- et al.
- 1997
- VLSI-TSA 1997
Floating body effects in partially-depleted SOI CMOS circuits
- P.F. Lu
- J. Ji
- et al.
- 1996
- LPED 1996
Floating body effects in partially-depleted SOI CMOS circuits
- P.F. Lu
- J. Ji
- et al.
- 1996
- LPED 1996