Low temperature SER and noise in a high speed DRAM
W.H. Henkels, N.C.-C. Lu, et al.
Workshop on Low Temperature Semiconductor Electronics 1989
This paper describes a test pattern for testing DRAM cell data retention that differs from conventional retention time tests. The test pattern is applicable to non-VDD bitline precharge designs, and is specifically designed to test for worst-case subthreshold leakage through the cell access device by holding bit lines in their latched position for extended periods. This action stresses the cell access devices with the worst-case VDSacross them. The reasons to perform this test on a DRAM are reviewed, its advantages over standard retention time tests are described, and its ability to differentiate access device leakage from isolation leakage is discussed. Measured results on a 1-Mb chip are shown, illustrating the test pattern’s effectiveness in screening subthreshold leakage. © 1992 IEEE
W.H. Henkels, N.C.-C. Lu, et al.
Workshop on Low Temperature Semiconductor Electronics 1989
R.A. Haring, M.S. Milshtein, et al.
VLSI Circuits 1996
Hyun J. Shin, P.F. Lu, et al.
ISSCC 1993
T.V. Rajeevakumar, Nicky C. C. Lu, et al.
IEEE Electron Device Letters