A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS

A highly modular digital PLL architecture is demonstrated by two DPLLs using distinct DCO designs for widely separated frequency ranges. In the PLLs, a common digital circuit controls the oscillator, a 1-to-2GHz 5-stage ring DCO in one and a 24-to-32GHz LC-tank DCO in the other. The common block uses the same 8b adder for the loop filter, the ΔΣ modulator, and the divider. The ring-DPLL has a second ΔΣ modulator for operation as a fractional-N synthesizer. The phase noise of the LC-DPLL at a 1MHz offset from 32GHz is -97dBc/Hz. The period jitter of the ring-DPLL at 2GHz is 1 psrms. ©2008 IEEE.