An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS
- A. Serdar Yonar
- Pier Andrea Francese
- et al.
- 2022
- VLSI Technology and Circuits 2022
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100 results for Herschel Ainspan
Automated Assembly of High Port Count Silicon Photonic Switches
- Nicolas Boyer
- Fuad Doany
- et al.
- 2020
- ECTC 2020
6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
- Zeynep Toprak-Deniz
- Jonathan E. Proesel
- et al.
- 2019
- ISSCC 2019
A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS
- Timothy O. Dickson
- Herschel Ainspan
- et al.
- 2017
- ISSCC 2017
A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2016
- ISSCC 2016
A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2015
- ISSCC 2015
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology
- John Bulzacchelli
- Troy Beukema
- et al.
- 2012
- ISSCC 2012
Bang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
- A. Rylyakov
- J. Tierno
- et al.
- 2009
- ISSCC 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
- John F. Bulzacchelli
- Timothy O. Dickson
- et al.
- 2009
- ISSCC 2009
A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- A. Rylyakov
- J. Tierno
- et al.
- 2008
- ISSCC 2008