Conference paper
A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
Kyu-Hyoun Kim, Paul W. Coteus, et al.
ISSCC 2008
Implemented in 65nm bulk CMOS, the 8.5Gb/s transmitter exhibits an eye height exceeding 1.0V and has a return loss of <-16dB up to 10GHz owing to the use of 40×40μm2 T-coils that are applied to the 1.5V-operated thick-oxide output slices. The equalization consists of a 5b 2-tap FIR filter whose adaptation is orthogonal to that of the impedance tuning. A duty-cycle restoration capability of 5x is achieved. The chip consumes 96mW at 8.5Gb/s and occupies 180×360μm2. ©2008 IEEE.
Kyu-Hyoun Kim, Paul W. Coteus, et al.
ISSCC 2008
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Optics Express
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