Jeng-Bang Yau, Jin Cai, et al.
Journal of Applied Physics
The variability of CMOS device propagation delay is measured with a special test circuit. The circuit detects AC delay variations, as distinct from the DC effect of threshold voltage variation. The AC variability is likely due to the vertical resistance of the gate-stack. A comparison of two technologies, using gate-first and gate-last gate-stacks, shows much reduced variability of the gate-last FETs. This is attributed to the absence of interfacial dopant fluctuation and the presence of tailored metallic interfaces in gate-last technologies.
Jeng-Bang Yau, Jin Cai, et al.
Journal of Applied Physics
Dinkar V. Singh, Keith A. Jenkins, et al.
IEEE TNANO
Keith A. Jenkins, James P. Eckhardt
IEEE Design and Test of Computers
Mark B. Ketchen, Manjul Bhushan, et al.
IEEE International SOI Conference 2005