Swagath Venkataramani, Jungwook Choi, et al.
PACT 2017
An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V. © 2008 IEEE.
Swagath Venkataramani, Jungwook Choi, et al.
PACT 2017
Shubham Jain, Swagath Venkataramani, et al.
DAC 2018
Brian L. Ji, Dale J. Pearson, et al.
ICMTS 2008
Leland Chang, David M. Fried, et al.
VLSI Technology 2005