Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2005
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2005
J.D. Cressler, D.D. Tang, et al.
ISSCC 1989
Rajiv Joshi, Rouwaida Kanj, et al.
ISLPED 2007
Ruchir Puri, Ching-Te Chuang
IEEE Journal of Solid-State Circuits