Chuteng Zhou, Fernando Garcia Redondo, et al.
IEEE Micro
The current trend for domain-specific architectures has led to renewed interest in research test chips to demonstrate new specialized hardware. Tapeouts also offer huge pedagogical value garnered from real hands-on exposure to the whole system stack. However, success with tapeouts requires hard-earned experience, and the design process is time consuming and fraught with challenges. Therefore, custom chips have remained the preserve of a small number of research groups, typically focused on circuit design research. This article describes the CHIPKIT framework: a reusable SoC subsystem which provides basic IO, an on-chip programmable host, off-chip hosting, memory, and peripherals. This subsystem can be readily extended with new IP blocks to generate custom test chips. Central to CHIPKIT is an agile RTL development flow, including a code generation tool called VGEN. Finally, we discuss best practices for full-chip validation across the entire design cycle.
Chuteng Zhou, Fernando Garcia Redondo, et al.
IEEE Micro
Paul N. Whatmough, Saekyu Lee, et al.
VLSI Circuits 2019
Sae Kyu Lee, Paul N. Whatmough, et al.
IEEE JSSC
Paul N. Whatmough, Saekyu Lee, et al.
VLSI Circuits 2019