A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
- Tianyu Jia
- Paolo Mantovani
- et al.
- 2022
- ESSCIRC 2022
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22 results for David Brooks
SMIV: A 16-nm 25-mm SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators
- Sae Kyu Lee
- Paul N. Whatmough
- et al.
- 2022
- IEEE JSSC
CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development
- Paul N. Whatmough
- Marco Donato
- et al.
- 2020
- IEEE Micro
Emerging Neural Workloads and Their Impact on Hardware
- David Brooks
- Martin M. Frank
- et al.
- 2020
- DATE 2020
A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators
- Paul N. Whatmough
- Saekyu Lee
- et al.
- 2019
- VLSI Circuits 2019
A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET
- Saekyu Lee
- Paul N. Whatmough
- et al.
- 2018
- ESSCIRC 2018
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
- Paul N. Whatmough
- Saekyu Lee
- et al.
- 2018
- IEEE JSSC
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
Co-designing accelerators and SoC interfaces using gem5-Aladdin
- Yakun Sophia Shao
- Sam Likun Xi
- et al.
- 2016
- MICRO 2016
Quantifying sources of error in McPAT and potential impacts on architectural studies
- Sam Likun Xi
- Hans Jacobson
- et al.
- 2015
- HPCA 2015