Conference paper
Simulation study of nanowire tunnel FETs
Andreas Schenk, Reto Rhyner, et al.
DRC 2012
Two different nanowire tunnel FETs, based either on the InAs/Si or the In0.53Ga0.47As/InP hetero-system, are investigated by device simulation. Variations of radius, equivalent oxide thickness, local doping, valence band offset, temperature, and the effect of trapassisted tunneling on the sub-threshold slope and the on-current of the transistors are demonstrated.
Andreas Schenk, Reto Rhyner, et al.
DRC 2012
Preksha Tiwari, Svenja Mauthe, et al.
IPC 2020
M. Scherrer, S. Kim, et al.
SPIE Nanoscience + Engineering 2021
Noelia Vico Triviño, Philipp Staudinger, et al.
PVLED 2019