David Daly, Peter Buchholz, et al.
Statistics and Probability Letters
To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance. © 2011 IEEE.
David Daly, Peter Buchholz, et al.
Statistics and Probability Letters
Janani Mukundan, Hillery Hunter, et al.
ISCA 2013
Mohammad Banikazemi, David Daly, et al.
LISA 2008
David Daly, Dong Ryu Kyung, et al.
WHPCF 2008