Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem
- Saravanan Sethuraman
- Venkata Kalyan Tavva
- et al.
- 2020
- IEEE TCADIS
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13 results for Hillery C. Hunter
BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy
- M. Cho
- Ulrich Finkler
- et al.
- 2019
- IBM J. Res. Dev
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
- Janani Mukundan
- Hillery Hunter
- et al.
- 2013
- ISCA 2013
Coordinating DRAM and last-level-cache policies with the virtual write queue
- Jeffrey Stuecheli
- Dimitris Kaseridis
- et al.
- 2011
- IEEE Micro
Elastic refresh: Techniques to mitigate refresh penalties in high density memory
- Jeffrey Stuechelixz
- Dimitris Kaseridis
- et al.
- 2010
- MICRO 2010
The Virtual Write Queue: Coordinating DRAM and last-level cache policies
- Jeffrey Stuecheli
- Dimitris Kaseridis
- et al.
- 2010
- ISCA 2010
Hardware-compiler co-design for adjustable data power savings
- Hillery C. Hunter
- Erik M. Nystrom
- et al.
- 2009
- Microprocessors and Microsystems
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits