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IBM J. Res. Dev
This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets. © 2006 IEEE.
David F. Heidel, Kenneth P. Rodbell, et al.
IBM J. Res. Dev
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IEEE TNS
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IRPS 2008