Conference paper
Within-chip variability analysis
S. Nassif
IEDM 1998
We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.
S. Nassif
IEDM 1998
A. Deutsch, H. Harrer, et al.
IEDM 1998
E. Burstein
Ferroelectrics
A.B. McLean, R.H. Williams
Journal of Physics C: Solid State Physics