Shireen Warnock, Rob Groves, et al.
CICC 2014
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Shireen Warnock, Rob Groves, et al.
CICC 2014
Siyu Koswatta, N. Mavilla, et al.
IEDM 2015
C. Kothandaraman, X. Chen, et al.
IRPS 2015
Tenko Yamashita, S. Mehta, et al.
VLSI Technology 2015