Investigations of silicon nano-crystal floating gate memories
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration. © 2014 Elsevier Ltd. All rights reserved.
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
William G. Van der Sluys, Alfred P. Sattelberger, et al.
Polyhedron
David B. Mitzi
Journal of Materials Chemistry
P. Martensson, R.M. Feenstra
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films