A. Hartstein, Thomas R. Puzak
Transactions on Architecture and Code Optimization
Double Al gate silicon MOSFETs have been fabricated with channel lengths ranging from 125 nm to 7.7 nm using a novel step/edge technique. The devices exhibit lateral tunneling between inversion layer source/drain extensions in the sub-threshold region and inversion layer conduction above threshold. At 0.45K and in devices shorter than 21 nm periodic oscillations are observed at bias voltages where the short-gate region is inverted. These are attributed to quantum interference arising from the ultra-short channel length. At bias voltages where the short gate region is in depletion, lateral tunneling is observed between the two inversion layer contacts. The lateral tunneling consists of a superposition of resonant tunneling peaks caused by defect states in the short channel region.
A. Hartstein, Thomas R. Puzak
Transactions on Architecture and Code Optimization
Thomas R. Puzak, A. Hartstein, et al.
CF 2007
A. Hartstein, J.R. Kirtley, et al.
Physical Review Letters
A. Hartstein, D.R. Young
Applied Physics Letters