Conference paper
Simulation study of nanowire tunnel FETs
Andreas Schenk, Reto Rhyner, et al.
DRC 2012
We have demonstrated the first InGaAs MOSFETs with sub-nm EOT featuring a gate-first implant-free process compatible with VLSI. At L G = 65 nm, these devices are among the best reported ones in terms of electrostatic integrity but they suffer from a large access resistance related to a large gate-to-source/drain spacing. Future work will focus on scaling this spacing in the 5 nm range in order to achieve the desired on-performance. © 2012 IEEE.
Andreas Schenk, Reto Rhyner, et al.
DRC 2012
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CLEO 2023
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IPC 2020
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