Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
IEEE Transactions on Electron Devices
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations. © 2006 IEEE.
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
IEEE Transactions on Electron Devices
G.P. Li, E. Hackbarth, et al.
IEEE T-ED
Chun-Yu Chen, Jyi-Tsong Lin, et al.
IEEE International SOI Conference 2010
Keunwoo Kim, Koushik K. Das, et al.
ISLPED 2004