L.K. Wang, A. Acovic, et al.
MRS Spring Meeting 1993
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node. ©2004 IEEE.
L.K. Wang, A. Acovic, et al.
MRS Spring Meeting 1993
Paul M. Solomon, Min Yang
IEDM 2004
Sharee J. McNab, Richard J. Blaikie
Materials Research Society Symposium - Proceedings
Yu-Ming Lin, Joerg Appenzeller, et al.
IEDM 2004