Conference paper
Timing analysis and optimization: From devices to systems
A. Devgan, Sandip Kundu
ASP-DAC 1998
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
A. Devgan, Sandip Kundu
ASP-DAC 1998
Sandip Kundu, Sudhakar M. Reddy, et al.
ICCAD 1987
Sandip Kundu
ISIT 1990
Sandip Kundu, I. Nair, et al.
European Conference on Design Automation 1992