William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
InGaAs is a promising alternative channel material to Si for sub-22 nm node technology because of its low electron effective mass (m*) hence high electron velocities. We report a gate-first MOSFET process with self-aligned source/drain formation using non-selective MBE re-growth, suitable for realizing high performance scaled III-V MOSFETs. A W/Cr/SiO2 gate stack was defined on thin (4 nm/2.5 nm) In-GaAs/InP channel by an alternating selective dry etch technique. A 5 nm Al2O3 layer was used as gate dielectric. An InAlAs bottom barrier provided vertical confinement of the channel. An in-situ H cleaning of the wafer leaves an epiready surface suitable for MBE or MOCVD regrowth. Source/Drain region were defined by non-selective MBE regrowth and in situ molybdenum contacts. First generation of devices fabricated using this process showed extremely low drive current of 2 μA/μm. The drive current was limited by an extremely high source resistance. A regrowth gap between source/drain and gate was the cause for high source resistance. The gap in the regrowth was because of low growth temperature (400 °C). A modified high temperature growth technique resolved the problem. © 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
Shaoning Yao, Wei-Tsu Tseng, et al.
ADMETA 2011
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
E. Burstein
Ferroelectrics