D. Singh, Keith A. Jenkins, et al.
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Measurement of history effect in PD/SOI single-ended CPL circuit
Abstract
Direct measurement of history effect in partially depleted silicon on insulator (PD/SOI) was discussed. The mechanism of the history effect in complementary pass-transistor logic (CPL) circuit was also analyzed. The results showed that the relative history effect of CPL gates increases as the supply voltage is lowered.
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