Modeling of spatial correlations in process, device, and circuit variations

We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA technique, we give a very compact expression to represent a given spatial correlations among a set of similar statistical variables/instances located at different places on a chip/die. Our compact expression is easy for implementation in a SPICE model and is efficient in circuit simulations.