On the connection of SRAM cell stability with switching history in partially depleted SOI technology

Read and write operational margins for SRAM cells in Partially Depleted Silicon on Insulator (PD-SOI) technology are studied. In both simulation and concept, cell stability is shown to be directly connected to the inverter nFET first switch/ second switch history, thus linking SRAM margins to a PD-SOI parameter that can be measured and monitored. © 2006 IEEE.