Optimization of 3nm High Performance Nanosheet Technology for 77 K Operation

We developed process and integration solutions for high-performance 3nm Gate-All-Around Nanosheet technology (54nm Contacted Poly-Pitch) at 77 K and assessed its performance advantages. This is the first demonstration of CMOS Nanosheet integration using dual work function metals (WFMs) and dual dipoles at 77 K. WFM and dual dipole engineering provide a targeted threshold voltage (Vt) solution for Nanosheet technology at this temperature. Nanosheets operating at low supply voltage VDD (0.3–0.4 V) at 77 K deliver performance comparable to 300 K operation at VDD=0.75V but with much lower power consumption. Additionally, Nanosheets at 77 K offer over 100% performance gain compared to 300 K at the same VDD=0.75V.