Modeling polarization for Hyper-NA lithography tools and masks
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
The device/circuit performance of strained-Si (SS) MOSFETs including strained-Si channel-on-insulator (SSOI) is assessed via a physics-based compact model calibrated against fabricated 70 nm strained and unstrained (control) Si devices. With emphasis on SS device specific features, mobility enhancement and band offsets, and SOI advantages, dynamic floating-body effects and no areal junction capacitance, the speed superiority of SSOI CMOS is discussed. Device design point and performance trade-off are presented as well, thus allowing exploitation of maximum performance in the SS devices. © 2003 Elsevier Ltd. All rights reserved.
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
Min Yang, Jeremy Schaub, et al.
Technical Digest-International Electron Devices Meeting
L.K. Wang, A. Acovic, et al.
MRS Spring Meeting 1993
William G. Van der Sluys, Alfred P. Sattelberger, et al.
Polyhedron