Modeling polarization for Hyper-NA lithography tools and masks
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130 nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits. © 2008 Elsevier Ltd. All rights reserved.
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
Revanth Kodoru, Atanu Saha, et al.
arXiv
A. Krol, C.J. Sher, et al.
Surface Science
Shiyi Chen, Daniel Martínez, et al.
Physics of Fluids