David M. Brooks, Pradip Bose, et al.
IEEE Micro
A 440 000-transistor second-generation RISC floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy is increased by using a floating-point multiply—add-fused (MAT) unit, which carries out a double-precision accumulate D = (A X B) + C as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS UNPACK). © 1990 IEEE
David M. Brooks, Pradip Bose, et al.
IEEE Micro
Hans M. Jacobson, Prabhakar N. Kudva, et al.
ASYNC 2002
Leland Chang, Robert K. Montoye, et al.
VLSI Circuits 2010
Tak H. Ning, Peter W. Cook, et al.
IEEE JSSC