Leland Chang, David J. Frank, et al.
Proceedings of the IEEE
A 440 000-transistor second-generation RISC floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy is increased by using a floating-point multiply—add-fused (MAT) unit, which carries out a double-precision accumulate D = (A X B) + C as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS UNPACK). © 1990 IEEE
Leland Chang, David J. Frank, et al.
Proceedings of the IEEE
Jayakumaran Sivagnaname, Hung C. Ngo, et al.
ISQED 2005
Leland Chang, Yutaka Nakamura, et al.
VLSI Circuits 2007
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IMW 2011