Silicon nanowire tunnel FETs: Low-temperature operation and influence of high-k gate dielectric

In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO2, Al 2O3, and HfO2, and show a performance enhancement when using high-k dielectric materials. The best performance is achieved for the devices using HfO2 as the gate dielectric, which reach an Ion of 0.1 μA/μm (VDS = - 0.5 V, V GS = - 2 V) , combined with an average inverse subthreshold slope (SS) of ∼120 mV/dec and an Ion/Ioff ratio of around 106. For the tunnel FETs with Al2O3 as the gate dielectric, different annealing steps were evaluated, and an activation anneal at only 700 °C} was found to yield the best results. Furthermore, we also investigated the temperature behavior of the tunnel FETs. Ideal tunnel FET behavior was observed for devices having ohmic Ni/Au contacts, and we demonstrate the invariance of both the SS and on-current with temperature, as expected for true tunnel FETs. © 2006 IEEE.