Steven E. Laux, Arvind Kumar, et al.
IEEE TNANO
We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability. © 2007 IEEE.
Steven E. Laux, Arvind Kumar, et al.
IEEE TNANO
Amlan Majumdar, Xinlin Wang, et al.
IEEE Electron Device Letters
Hao Lin, Haitao Liu, et al.
LEC 2006
Wilfried Haensch, Edward J. Nowak, et al.
IBM J. Res. Dev