A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- ISSCC 2024
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
- Ram Krishna
- Atom O. Watanabe
- et al.
- 2023
- ECTC 2023
Thermal Characterization of 3-D Stacked Heterogeneous Integration (HI) Package for High-Power Computing Applications
- Aakrati Jain
- Risa Miyazawa
- et al.
- 2023
- ECTC 2023
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh
- Shubham Jain
- Hsinyu Tsai
- et al.
- 2023
- IEEE Transactions on VLSI Systems
A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network
- Ram Krishna
- Thong Nguyen
- et al.
- 2022
- EDAPS 2022
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
A Simple, unified 3D stress model for device design in stress-enhanced mobility technologies
- Arvind Kumar
- Kai Xiu
- et al.
- 2012
- SISPAD 2012
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- Q. Liu
- Frederic Monsieur
- et al.
- 2011
- VLSI Technology 2011