Dieter F. Wendel, Ron Kalla, et al.
IEEE Journal of Solid-State Circuits
The clock distribution of the Power4 microprocessor was studied. This distribution on the Power4 supplies a single critical 1.5 GHz clock from one SOI-optimized phase locked loop (PLL) to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.
Dieter F. Wendel, Ron Kalla, et al.
IEEE Journal of Solid-State Circuits
Peilin Song, Franco Stellari, et al.
ISTFA 2004
Sophie Verdonckt-Vandebroek, Bernard S. Meyerson, et al.
IEEE Transactions on Electron Devices
Phillip J. Restle, Craig A. Carter, et al.
ISSCC 2002