NanoStack Transistor Architecture for CMOS 7A Node and Beyond
Shay Reboh, Chen Zhang, et al.
VLSI Technology and Circuits 2025
For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub-nanometer accuracy. Due to the projection effect of TEM technique, comprehensive understanding of the 3D structure from 2D images is needed for process development of FinFET. This paper will address sample preparations and TEM imaging techniques for FinFET device at sub-100nm pitch. Copyright © 2011 ASM International®. All rights reserved.
Shay Reboh, Chen Zhang, et al.
VLSI Technology and Circuits 2025
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Applied Physics Letters
S.C. Lai, S. Kim, et al.
VLSI Technology 2013
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Advanced Functional Materials