Conference paper
Visualizing computer memory architectures
Bowen Alpern, Larry Carter, et al.
Visualization 1990
The testability by random test patterns of faults in the logic surrounding embedded RAM's is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM. © 1988 IEEE
Bowen Alpern, Larry Carter, et al.
Visualization 1990
Larry Carter, Leendert M. Huisman, et al.
IEEE ITC 1985
Larry Carter, Leendert M. Huisman, et al.
IEEE ITC 1985
Leendert M. Huisman, Raja Daoud, et al.
DMCC 1990